Modern computer architectures typically provide a mechanism, such as an effective to real address translation (ERAT) table, for converting an effective address (EA), used by an application, to a real address (RA), which is used for referencing memory. In order for applications to be able to execute quickly, it is important that the EA to RA translation be done as efficiently as possible.
The ERAT table is usually based on a specific page size, known as the base page size. In conventional systems, the use of page sizes larger than the base page typically results in multiple entries in the ERAT table for the same page. For example, if the base page size is 4 kilobytes (KB), an entry for a 4 KB page would use one ERAT entry, an 8 KB page would use two entries and a 16 KB page would use four entries in the ERAT table.
It is possible for very large page sizes, such as 16 megabytes (MB) or greater, for one page to use up all entries in the ERAT. This is very wasteful of ERAT entries, and can result in slower performance when an address on a page that is not in the ERAT table is accessed, resulting in the EA being sent to a higher level of address translation, which usually takes significantly longer than an ERAT lookup.
Therefore, there is a need for a more efficient method of handling multiple page sizes when using an ERAT table.